Overcoming the Fermi-Level Pinning Effect in the Nanoscale Metal and Silicon Interface

Area of Science:

• Materials Science
• Electrical Engineering
• Optoelectronics

Background:

• Silicon-based photodetectors offer cost-effectiveness and CMOS compatibility for silicon photonics.
• Extending silicon photodetector responsivity to the mid-infrared (mid-IR) range is a significant challenge.
• Fermi-level pinning and metal-induced gap states (MIGS) at metal/silicon interfaces hinder mid-IR performance.

Purpose of the Study:

• To mitigate Fermi-level pinning in silicon-based photodetectors for enhanced mid-IR responsivity.
• To demonstrate the effectiveness of a passivated surface layer in metal-insulator-semiconductor (MIS) contacts.
• To improve the performance of Schottky detectors for broader wavelength detection.

Main Methods:

• Fabrication of metal-insulator-semiconductor (MIS) structures using a passivated semiconductor surface layer.
• Utilizing the insulating layer to mitigate the Fermi-level pinning effect at the metal/semiconductor interface.
• Characterization of photodetector responsivity and detectivity across the mid-IR spectrum.

Main Results:

• Successfully reduced the Schottky barrier height by 12.5% to 16% through the removal of Fermi-level pinning.
• Achieved high responsivity: 234 μA/W at 2 μm, 48.2 μA/W at 3 μm, and 1.75 μA/W at 6 μm.
• Obtained high detectivities: 1.17 × 10^8 cm Hz^(1/2) W^(-1) at 2 μm and 2.41 × 10^7 cm Hz^(1/2) W^(-1) at 3 μm.

Conclusions:

• The passivated surface layer effectively mitigates Fermi-level pinning in silicon photodetectors.
• The developed MIS photodetectors exhibit significantly improved responsivity and detectivity in the mid-IR range.
• This advancement broadens the sensing capabilities of silicon photonics platforms for future applications.