Jove
Visualize
Contact Us

Related Concept Videos

PD Controller: Design01:26

PD Controller: Design

278
In automotive engineering, car suspension systems often employ Proportional Derivative (PD) controllers to enhance performance. PD controllers are utilized to adjust the damping force in response to road conditions. A controller, acting as an amplifier with a constant gain, demonstrates proportional control, with output directly mirroring input.
Designing a continuous-data controller requires selecting and linking components like adders and integrators, which are fundamental in Proportional,...
278
PI Controller: Design01:24

PI Controller: Design

329
Proportional Integral (PI) controllers are a fundamental component in modern control systems, widely used to enhance performance and mitigate steady-state errors. They are particularly effective in applications such as automatic brightness adjustment on smartphones, where they excel at mitigating steady-state errors for step-function inputs. Unlike PD controllers, which require time-varying errors to function optimally, PI controllers leverage their integral component to address residual...
329

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by
Same author

SSPRD: A Shared-Storage-Based Hardware Packet Reordering and Deduplication System for Multipath Transmission in Wide Area Networks.

Micromachines·2024
Same author

High-Performance Reconfigurable Pipeline Implementation for FPGA-Based SmartNIC.

Micromachines·2024
Same author

QGWFQS: A Queue-Group-Based Weight Fair Queueing Scheduler on FPGA.

Micromachines·2023
Same journal

Correction: Kang et al. Fluid Flow to Electricity: Capturing Flow-Induced Vibrations with Micro-Electromechanical-System-Based Piezoelectric Energy Harvester. <i>Micromachines</i> 2024, <i>15</i>, 581.

Micromachines·2026
Same journal

Femtosecond Laser Texturing of Wood Coatings with Bio-Based Epoxy and Wax Additives for Enhanced Hydrophobicity.

Micromachines·2026
Same journal

Engineering of Optoelectronic Devices for Renewable Energy Applications.

Micromachines·2026
Same journal

Phase Transformation and Electrochemical Behavior of Hexagonal TiO<sub>2</sub> Nanotubes Under Different Annealing Temperatures and Heating Rates.

Micromachines·2026
Same journal

Process Optimization and Predictive Modeling of Femtosecond Laser Precision Milling for Commercial PMMA Slices.

Micromachines·2026
Same journal

A Hybrid Preprocessing Multi-Objective Surrogate Model for Thermal MEMS Actuators.

Micromachines·2026
See all related articles
JoVE
x logofacebook logolinkedin logoyoutube logo
ABOUT JoVE
OverviewLeadershipBlogJoVE Help Center
AUTHORS
Publishing ProcessEditorial BoardScope & PoliciesPeer ReviewFAQSubmit
LIBRARIANS
TestimonialsSubscriptionsAccessResourcesLibrary Advisory BoardFAQ
RESEARCH
JoVE JournalMethods CollectionsJoVE Encyclopedia of ExperimentsArchive
EDUCATION
JoVE CoreJoVE BusinessJoVE Science EducationJoVE Lab ManualFaculty Resource CenterFaculty Site
Terms & Conditions of Use
Privacy Policy
Policies

Related Experiment Video

Updated: Jul 18, 2025

Design and Synthesis of a Reconfigurable DNA Accordion Rack
07:44

Design and Synthesis of a Reconfigurable DNA Accordion Rack

Published on: August 15, 2018

7.1K

The Design of a Dynamic Configurable Packet Parser Based on FPGA.

Ying Sun1,2, Zhichuan Guo1,2

  • 1National Network New Media Engineering Research Center, Institute of Acoustics, Chinese Academy of Sciences, No. 21, North Fourth Ring Road, Haidian District, Beijing 100190, China.

Micromachines
|August 26, 2023
PubMed
Summary
This summary is machine-generated.

We developed a dynamic, low-latency FPGA parser for programmable networks, overcoming traditional parser limitations. This adaptable solution achieves high throughput and minimal latency for efficient network data processing.

Keywords:
FPGAdynamic configurablelow lantencypacket parser

More Related Videos

Generation of Dynamical Environmental Conditions using a High-Throughput Microfluidic Device
14:48

Generation of Dynamical Environmental Conditions using a High-Throughput Microfluidic Device

Published on: April 17, 2021

4.1K
High-precision Electromagnetic Flowmeter with Empty Pipe Detection via Complex Programmable Logic Device-based Waveform Recognition
05:11

High-precision Electromagnetic Flowmeter with Empty Pipe Detection via Complex Programmable Logic Device-based Waveform Recognition

Published on: June 27, 2025

55

Related Experiment Videos

Last Updated: Jul 18, 2025

Design and Synthesis of a Reconfigurable DNA Accordion Rack
07:44

Design and Synthesis of a Reconfigurable DNA Accordion Rack

Published on: August 15, 2018

7.1K
Generation of Dynamical Environmental Conditions using a High-Throughput Microfluidic Device
14:48

Generation of Dynamical Environmental Conditions using a High-Throughput Microfluidic Device

Published on: April 17, 2021

4.1K
High-precision Electromagnetic Flowmeter with Empty Pipe Detection via Complex Programmable Logic Device-based Waveform Recognition
05:11

High-precision Electromagnetic Flowmeter with Empty Pipe Detection via Complex Programmable Logic Device-based Waveform Recognition

Published on: June 27, 2025

55

Area of Science:

  • Computer Engineering
  • Network Architecture
  • Hardware Acceleration

Background:

  • Traditional fixed-type protocol parsers struggle to meet the dynamic demands of modern programmable networks.
  • Existing solutions often face limitations in latency and configurability, hindering network flexibility.

Purpose of the Study:

  • To propose a dynamic and configurable low-latency parser implemented on Field-Programmable Gate Arrays (FPGAs).
  • To enhance network adaptability and efficiency by addressing the limitations of conventional protocol parsers.

Main Methods:

  • Designed an FPGA architecture featuring three protocol analysis modules and TCAM-SRAM for efficient data processing.
  • Optimized state machine and parallel extraction matching to reduce latency.
  • Introduced chain mapping and container concepts for flexible rule formulation and enhanced parser extensibility, with dynamic configuration via Software-Defined Networking (SDN).

Main Results:

  • Achieved a throughput exceeding 80 Gbps on Xilinx Ultrascale+ FPGAs.
  • Demonstrated a maximum latency of only 36 nanoseconds for Layer 4 (L4) protocol parsing.
  • Verified and simulated the design using a cocotb-based framework.

Conclusions:

  • The proposed dynamic FPGA parser offers a low-latency, high-throughput solution for programmable networks.
  • The architecture provides flexible adaptation to diverse network scenarios through dynamic SDN control.
  • This approach significantly improves upon the limitations of traditional fixed-type protocol parsers.