Determining Stress in Metallic Conducting Layers of Microelectronics Devices Using High Resolution Electron...

Area of Science:

• Materials Science
• Microelectronics Reliability
• Solid Mechanics

Background:

• Aging microelectronics face delayed failure due to stress voiding, where voids can cause open circuits.
• Accurate stress measurement in metallic layers is vital for predicting this failure mode.
• Direct stress measurement is challenging as exposing conductive lines relieves stress.

Purpose of the Study:

• To develop and validate a novel technique for measuring internal stresses in microelectronic metallic layers.
• To investigate stress distribution in legacy microelectronic components, with and without visible voids.
• To provide a method for comparing experimental stress data with theoretical stress voiding models.

Main Methods:

• Mechanical thinning of the device substrate to access internal layers.
• High-resolution electron backscatter diffraction (HREBSD) to measure surface distortions on the thinned substrate.
• Finite element analysis (FEA) to correlate substrate distortions with subsurface stresses in metallic layers.

Main Results:

• Stresses in legacy components without apparent voids were found to be approximately 300 MPa, matching theoretical manufacturing stresses.
• Distortion fields around known voids were successfully mapped, providing data for direct comparison with stress voiding models.
• The HREBSD technique, combined with FEA, effectively infers subsurface stresses in layered microelectronic devices.

Conclusions:

• The presented HREBSD coupled with FEA is a valuable non-destructive technique for assessing stress and predicting failure in microelectronics.
• This method allows for the characterization of stress states in aging components, crucial for reliability assessments.
• The ability to map distortion fields around voids offers new avenues for validating and refining stress voiding failure models.