Design and Implementation of a Highly Efficient Quasi-Cyclic Low-Density Parity-Check Transceiving System Using an...

Area of Science:

• Information Theory
• Digital Communications
• Computer Engineering

Background:

• Traditional Low-Density Parity-Check (LDPC) encoding and decoding systems suffer from low throughput and high resource demands.
• These limitations make them unsuitable for cost-efficient, energy-saving sensor networks.

Purpose of the Study:

• To optimize coding complexity and throughput for LDPC systems.
• To develop a combined design of a novel LDPC code structure and overlapping decoding strategies.

Main Methods:

• Constructed a CCSDS-like quasi-cyclic parity check matrix (PCM) for maximized overlap and parallel decoding.
• Employed a modified 2-bit Min-Sum algorithm (MSA) for decoding, achieving a 5 dB coding gain at a 10-6 BER.
• Implemented a shift-register-based memory scheduling strategy to leverage quasi-cyclic properties and reduce latency.

Main Results:

• The modified MSA decoder achieved a 5 dB coding gain compared to uncoded BPSK at a 10-6 BER.
• Overlap scheduling reduced time consumption by one-third per iteration.
• The decoder reached a throughput of 7.76 Gbps at 156.25 MHz with two-thirds resource savings.

Conclusions:

• The proposed LDPC code structure and overlapping decoding strategies significantly improve efficiency.
• This optimized design is well-suited for resource-constrained sensor networks.
• The system demonstrates high throughput and reduced resource consumption, validating its effectiveness.