Vertically Integrated CMOS Ternary Logic Device with Low Static Power Consumption and High Packing Density.

Area of Science:

• Semiconductor device physics
• Multivalued logic systems
• Energy-efficient computing architectures

Background:

• Binary logic systems face limitations in energy efficiency and transistor count.
• Multivalued logic offers a path to simpler architectures and reduced power consumption.
• Ternary logic requires devices capable of harnessing three stable states.

Purpose of the Study:

• To demonstrate a novel vertically integrated complementary metal-oxide-semiconductor ternary logic device.
• To achieve energy efficiency and reduced footprint in ternary logic systems.
• To explore the potential of integrating thin-film transistors (TFTs) over transistor-based threshold switches (TTSs).

Main Methods:

• Monolithic integration of a TFT over a TTS to create a hybrid device.
• Utilizing the distinct on- and off-states of the TFT and TTS to achieve three logic states (0, 1, 2).
• Electrical characterization to verify device functionality and performance metrics.

Main Results:

• Demonstration of a four-electrode ternary logic device (S, D, G_TFT, G_TTS) by electrically tying the drain of the TTS to the source of the TFT.
• Realization of low, middle, and high current states corresponding to ternary logic values 0, 1, and 2.
• Significant reduction in static power consumption at the "1"-state due to the TTS's low off-state leakage current.
• Approximately twofold reduction in device footprint compared to laterally deployed structures.

Conclusions:

• The demonstrated vertically integrated ternary logic device offers enhanced energy efficiency and a reduced footprint.
• The hybrid TFT-over-TTS architecture provides a promising pathway for simpler and more power-efficient multivalued logic systems.
• This approach has the potential to advance the development of next-generation computing architectures.