A Low-Latency DNN Accelerator Enabled by DFT-Based Convolution Execution Within Crossbar Arrays.

Area of Science:

• Materials Science
• Computer Engineering
• Artificial Intelligence

Background:

• Analog resistive random-access memory (RRAM) enables efficient in-memory computing for neural networks, overcoming von Neumann architecture limitations.
• However, the high tuning time for RRAM conductance states introduces latency in real-time training.
• Existing methods face challenges in balancing performance, power, and memory endurance.

Purpose of the Study:

• To develop a discrete Fourier transform (DFT)-based in-memory convolution methodology for analog RRAM.
• To reduce system latency and input regeneration in neural network accelerators.
• To minimize RRAM conductance updates, thereby enhancing training speed and device endurance.

Main Methods:

• Storing static DFT/inverse DFT (IDFT) coefficients within analog RRAM arrays.
• Performing convolution in the Fourier domain to minimize digital computations.
• Leveraging DFT/IDFT properties like symmetry and linearity for optimization.

Main Results:

• Significantly accelerated neural network training and inference by minimizing connection weight updates.
• Reduced power consumption for convolution operations compared to conventional methods.
• Enhanced peak power efficiency and area efficiency in the designed hardware accelerator.

Conclusions:

• The developed DFT-based RRAM methodology offers a pathway to ultrafast, low-power, and compact hardware accelerators.
• Minimizing RRAM conductance update frequency mitigates endurance limitations.
• This approach enables efficient edge deployment of deep neural networks with reduced latency and energy consumption.