Silicon-van der Waals heterointegration for CMOS-compatible logic-in-memory design

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Engineering

Background:

• Silicon CMOS-based computing-in-memory faces challenges in nonvolatility and reconfigurability for logic-in-memory applications.
• Existing designs struggle with power efficiency and complex integration.

Purpose of the Study:

• To introduce a universal design for nonvolatile, reconfigurable devices using 2D/3D heterointegration.
• To address the limitations of current computing-in-memory architectures.

Main Methods:

• Utilized van der Waals heterostacking with photo-controlled charge trapping/detrapping.
• Employed a partially top-gated energy band landscape for logic reconfigurability.
• Investigated dynamic charge fluctuations and trap levels.

Main Results:

• Achieved precise polarity tunability and logic nonvolatility.
• Demonstrated robustness at 85°C with a near-ideal subthreshold swing (80 mV dec⁻¹).
• Cascaded units into a monolithic circuit layer, showing high-gain logic gates (65 at Vdd = 0.5 V).

Conclusions:

• The 2D/3D heterointegrated design offers a promising prototype for future computing-in-memory hardware.
• This approach overcomes key design and power challenges in silicon CMOS technology.
• The developed devices exhibit excellent performance and stability for logic-in-memory operations.