A Flexible System-on-Chip Field-Programmable Gate Array Architecture for Prototyping Experimental Global Navigation...

Area of Science:

• Electrical Engineering
• Computer Engineering
• Aerospace Engineering

Background:

• Global Navigation Satellite System (GNSS) technology is advancing rapidly, necessitating agile research and development tools.
• Increasing complexity of GNSS integrated circuits (ICs) limits researchers' ability to modify or inspect receiver internals.
• Existing prototyping methods may lack the flexibility or efficiency required for cutting-edge GNSS research.

Purpose of the Study:

• To design and present a low-cost System-on-Chip Field-Programmable Gate Array (SoC-FPGA) architecture for experimental GNSS receiver prototyping.
• To enable the development of compact, portable, multi-channel, and multi-constellation GNSS receivers.
• To provide a flexible platform for testing novel and non-standard GNSS features with live signals.

Main Methods:

• Developed a System-on-Chip Field-Programmable Gate Array (SoC-FPGA) architecture.
• Integrated Software-Defined Radio (SDR) techniques with FPGA energy efficiency.
• Designed and evaluated a general-purpose GNSS receiver as a research testbed.

Main Results:

• Demonstrated the ability to acquire and track GNSS signals in static and low Earth orbit (LEO) scenarios.
• Assessed the quality of navigation observables.
• Evaluated the accuracy of navigation solutions derived from the prototype receiver.

Conclusions:

• The proposed SoC-FPGA architecture offers a flexible and efficient solution for prototyping advanced GNSS receivers.
• The developed testbed receiver successfully acquires and tracks GNSS signals, validating its performance for research applications.
• This approach facilitates the exploration of innovative GNSS functionalities and system designs.