Analog Convolutional Operator Circuit for Low-Power Mixed-Signal CNN Processing Chip.

Area of Science:

• Electrical Engineering
• Computer Engineering
• Artificial Intelligence Hardware

Background:

• Convolutional Neural Networks (CNNs) are crucial for AI, but their processing chips consume significant power and area, primarily due to convolutional operators.
• Multiply-accumulate (MAC) units are central to CNN computations, driving the need for efficient hardware implementations.

Purpose of the Study:

• To propose a compact and low-power mixed-signal approach for implementing convolutional operators in CNN processing chips.
• To reduce the chip area and power consumption associated with MAC units in CNN hardware.

Main Methods:

• Developed a mixed-signal convolutional operator using low-power binary-weighted current steering digital-to-analog converters (DACs) and accumulation capacitors.
• Integrated a novel charge-sharing technique for handling negative MAC results and an analog max-pooling circuit.
• Implemented a CNN processing chip with analog convolutional operators, MAC circuits, and an analog max-pooling unit using a 55 nm CMOS process.

Main Results:

• The proposed mixed-signal CNN chip achieved a silicon area of 0.0559 mm² and consumed 540.6 μW.
• Demonstrated significant reductions: 84.21% in area and 91.85% in energy compared to conventional digital CNN chips.
• The analog convolutional operator offers improved accuracy, smaller area, and lower power consumption due to its symmetric design.

Conclusions:

• The proposed mixed-signal convolutional operator provides a viable, low-power, and area-efficient alternative to digital implementations in CNNs.
• This approach can be widely adapted for various CNN models, paving the way for more efficient AI hardware.
• The developed analog MAC units and circuits represent a significant advancement in energy-efficient AI processing.