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Optimal Architecture of Floating-Point Arithmetic for Neural Network Training Processors.

Muhammad Junaid1, Saad Arslan2, TaeGeon Lee1

  • 1Department of Electronics, College of Electrical and Computer Engineering, Chungbuk National University, Cheongju 28644, Korea.

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Summary
This summary is machine-generated.

This study introduces an optimized mixed-precision accelerator for Artificial Intelligence of Things (AIoT) devices, enabling efficient on-device training and inference. The new design significantly reduces size and energy consumption while maintaining high accuracy for edge AI applications.

Keywords:
IEEE 754MNIST datasetconvolutional neural network (CNN)floating-points

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Area of Science:

  • Computer Engineering
  • Artificial Intelligence
  • Hardware Acceleration

Background:

  • Artificial Intelligence (AI) and the Internet of Things (AIoT) are key drivers of the fourth industrial revolution.
  • Current AIoT research focuses on inference accelerators, but training capabilities are increasingly needed for self-supervised and semi-supervised learning.
  • High-precision floating-point operations for training demand significant area and energy, posing challenges for edge devices.

Purpose of the Study:

  • To develop an energy-efficient and compact accelerator for AIoT devices capable of both inference and training.
  • To investigate optimal floating-point formats (32, 24, 16 bits, and mixed precision) for low-power, small-sized edge applications.
  • To achieve high accuracy in neural network training and inference on edge devices.

Main Methods:

  • Proposed a novel accelerator architecture incorporating mixed-precision floating-point training (32, 24, 16 bits).
  • Verified accelerator performance on FPGA for inference and training using the MNIST dataset.
  • Implemented the optimized mixed-precision accelerator on ASIC (TSMC 65nm) for area and energy analysis.

Main Results:

  • Achieved over 93% accuracy using a combination of 24-bit custom FP and 16-bit Brain FP formats.
  • ASIC implementation showed an active area of 1.036 × 1.036 mm² and 4.445 µJ energy consumption per image training.
  • Reduced size by 4.7 times and energy consumption by 3.91 times compared to 32-bit architectures.

Conclusions:

  • The optimized mixed-precision accelerator significantly reduces area and energy consumption for AIoT edge devices.
  • This architecture supports high-accuracy training and inference, crucial for advancing AIoT applications.
  • The proposed CNN structure with an optimized data path is vital for developing compact, low-power, high-accuracy AIoT solutions.