GAHLS: an optimized graph analytics based high level synthesis framework.

Area of Science:

• Computer Engineering
• Hardware Acceleration
• Algorithm Optimization

Background:

• The increasing demand for on-board intelligence in autonomous systems, robotics, and edge computing necessitates efficient specialized hardware with reconfigurability.
• Current systems face challenges in balancing low latency, high compute power, and low energy consumption for complex data science tasks.

Purpose of the Study:

• To propose a novel Graph Analytics based High Level Synthesis (GAHLS) framework for optimizing hardware accelerators.
• To efficiently analyze complex high-level programs and synthesize them into message-passing domain-specific accelerators.

Main Methods:

• Constructing a compiler-assisted dependency graph (CaDG) from LLVM IR and converting it into a hardware-friendly representation.
• Performing memory design space exploration and optimizing for higher bandwidth based on CaDG properties.
• Identifying and aggregating similar computational structures within the CaDG into intelligent processing clusters for optimized hardware resource utilization.

Main Results:

• The GAHLS framework synthesizes compressed, specialized CaDGs into processing elements, optimizing system performance and area.
• Evaluations on real-life applications, including deep learning and brain-machine interfaces, show significant improvements.
• Demonstrated 14.27x performance enhancement compared to state-of-the-art methods like LegUp 6.2.

Conclusions:

• The GAHLS framework offers a powerful approach for designing efficient hardware accelerators for demanding computational tasks.
• This method effectively addresses the need for low-latency, high-compute, and low-power on-board intelligence in advanced computing systems.
• The framework's ability to optimize hardware through graph analytics and synthesis provides a substantial performance leap over existing solutions.