Oxide Semiconductor Heterojunction Transistor with Negative Differential Transconductance for Multivalued Logic...

Area of Science:

• Semiconductor Physics
• Materials Science
• Electronics Engineering

Background:

• Multivalued logic (MVL) technology offers advantages in data density and power efficiency over traditional complementary metal-oxide-semiconductor (CMOS) technology.
• Heterojunction transistors (TRs) with negative differential transconductance (NDT) are crucial for MVL circuits but often use materials incompatible with CMOS processes.

Purpose of the Study:

• To develop an oxide semiconductor (OS) heterojunction transistor with NDT characteristics compatible with conventional CMOS manufacturing.
• To demonstrate the feasibility of using this transistor in MVL circuits.

Main Methods:

• Fabrication of a heterojunction transistor using p-type copper(I) oxide (Cu₂O) and n-type indium gallium zinc oxide (IGZO).
• Characterization of the electrical properties, including on/off ratio, NDT range, and peak-to-valley current ratio (PVCR).
• Analysis of device operation by varying device geometry and layer thickness, and demonstration of a ternary inverter.

Main Results:

• The fabricated OS heterojunction TR exhibits a high on/off ratio (∼3 × 10³), wide NDT range (∼29 V), and high PVCR (≈ 25).
• Uniform device performance was confirmed across multiple fabricated devices.
• A ternary inverter demonstrated three distinct logic states with improved error margins due to the device's NDT characteristics.

Conclusions:

• The developed oxide semiconductor heterojunction transistor with NDT characteristics is compatible with conventional CMOS processes.
• This technology shows significant potential for advancing MVL circuits by enhancing data density and reducing power consumption.