Parallel implement of real-time delta-sigma modulation for digital mobile fronthaul

Area of Science:

• Electrical Engineering
• Telecommunications
• Signal Processing

Background:

• Digital mobile fronthaul requires high-speed, efficient signal digitization.
• Traditional delta-sigma modulation (DSM) architectures face limitations with feedback loops and critical paths, hindering high sampling rates.
• Existing parallel DSM schemes can demand significant storage resources.

Purpose of the Study:

• To propose and experimentally validate a novel FPGA-based parallel architecture for delta-sigma modulation (DSM).
• To overcome the limitations of conventional DSM feedback loops and critical path constraints.
• To enable high sampling rates at lower hardware operating speeds for digital mobile fronthaul.

Main Methods:

• Developed a novel FPGA-based parallel architecture for delta-sigma modulation (DSM).
• Implemented a bit-by-bit quantization approach to minimize buffering requirements.
• Built and tested a real-time experimental system using a Xilinx Kintex Ultrascale FPGA.

Main Results:

• Successfully digitized 14 carrier aggregated orthogonal frequency division multiplexing (OFDM) signals into a 5Gb/s PAM4 signal.
• Transmitted the digitized signal over 20 km of single-mode fiber (SMF).
• Demonstrated waveform-agnostic digitization with 14 carrier aggregated filter-bank-multicarrier (FBMC) signals, achieving improved EVM performance.

Conclusions:

• The proposed FPGA-based parallel DSM architecture is feasible and effective for digital mobile fronthaul.
• The architecture supports high sampling rates and parallel processing efficiently, overcoming traditional DSM limitations.
• This approach offers a waveform-agnostic interface with potential for superior performance in telecommunication systems.