An FPGA implementation of Bayesian inference with spiking neural networks

Area of Science:

• Neuroscience and Computer Engineering
• Development of brain-inspired computing architectures
• Hardware acceleration for artificial intelligence

Background:

• Spiking Neural Networks (SNNs) offer efficient, low-complexity information processing inspired by the brain.
• Traditional von Neumann architectures limit SNN performance, driving demand for dedicated hardware.
• Probabilistic sampling in SNNs enables Bayesian inference but is computationally intensive.

Purpose of the Study:

• To design and implement a hardware accelerator for Spiking Neural Networks (SNNs) to expedite Bayesian inference.
• To overcome computational bottlenecks in SNN sampling models through hardware optimization.
• To leverage Field-Programmable Gate Arrays (FPGAs) for efficient SNN acceleration in embedded systems.

Main Methods:

• Designed a Field-Programmable Gate Array (FPGA) based hardware accelerator for SNNs.
• Employed streaming pipelining and array partitioning for efficient parallelization and resource optimization.
• Utilized the Python Productivity for Zynq (PYNQ) framework for model migration and acceleration on FPGA.

Main Results:

• The FPGA hardware accelerator significantly improved the computing speed of SNN sampling models.
• Inference accuracy was maintained while achieving substantial performance gains.
• The PYNQ framework facilitated the optimization of FPGA's high performance and low power consumption.

Conclusions:

• The proposed FPGA implementation of Bayesian inference with SNNs offers a significant speedup for complex probabilistic model inference.
• This approach is well-suited for resource-constrained embedded applications requiring high performance and low power.
• The hardware accelerator demonstrates great potential for a wide range of SNN-based applications.