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Logical Resolving-Based Methodology for Efficient Reliability Analysis.

Zhengguang Tang1, Cong Li1, Hailong You1

  • 1School of Microelectronics, Xidian University, Xi'an 710071, China.

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|January 23, 2024
PubMed
Summary
This summary is machine-generated.

This study introduces an improved method for analyzing aging effects in digital circuits, enhancing accuracy and speed. It addresses device aging dependence to prevent performance degradation and ensure reliability.

Keywords:
bias temperature instability (BTI)reliability simulation accelerationstatic timing analysisstress probability evaluation

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Area of Science:

  • Electrical Engineering
  • Computer Engineering
  • Materials Science

Background:

  • Deep nanoscale CMOS technology scaling exacerbates device aging effects, degrading circuit performance and potentially causing functional failure.
  • Reliability-aware circuit analysis is crucial for evaluating aging's impact, but existing methods overlook device aging dependence, leading to inaccurate degradation assessments.
  • Accurate stress analysis is vital for predicting and mitigating the effects of aging in modern integrated circuits.

Purpose of the Study:

  • To propose an improved analytical method for reliability-aware static timing analysis that accounts for device aging dependence.
  • To enhance the accuracy of aging path delay evaluation in digital circuits.
  • To reduce pessimism in aging timing evaluations and minimize performance sacrifices in aging-aware synthesis flows.

Main Methods:

  • An improved analytical method employing logical resolving is proposed to address device aging dependence.
  • The method focuses on improving the accuracy of reliability-aware static timing analysis.
  • Experimental validation compares the proposed method against traditional strategies and precise SPICE simulations.

Main Results:

  • The proposed method demonstrates superior accuracy in evaluating aging path delay compared to traditional strategies.
  • Excessive pessimism in aging timing evaluation is reduced.
  • A significant 378x speedup is achieved with only a 0.56% relative error compared to SPICE simulations.
  • Circuit performance sacrifice in aging-aware synthesis flows is decreased.

Conclusions:

  • The proposed analytical method significantly improves the accuracy and efficiency of reliability-aware static timing analysis for deep nanoscale CMOS circuits.
  • By considering device aging dependence, the method provides more reliable degradation evaluations and reduces pessimism.
  • The high efficiency and accuracy make the method suitable for large-scale digital circuit reliability analysis, meeting speed demands while maintaining transistor-level simulation accuracy.