Formation techniques for upper active channel in monolithic 3D integration: an overview.

Area of Science:

• Semiconductor device physics and fabrication
• Materials science for microelectronics
• 3D integrated circuit design

Background:

• Scaling down traditional semiconductor devices is increasingly difficult.
• Monolithic 3D (M3D) integration enables higher connection density compared to through-silicon vias.
• M3D integration faces significant technological hurdles for commercialization.

Purpose of the Study:

• To provide an overview of potential technologies for forming active channel layers in the upper device layers of M3D integration.
• To address the primary challenge of thermal budget limitations in M3D fabrication.
• To explore solutions for complementary metal-oxide-semiconductor (CMOS) devices and digital circuits.

Main Methods:

• Review of existing and emerging techniques for upper active channel layer formation.
• Analysis of thermal budget constraints for top-layer device processing.
• Investigation of materials including polysilicon, single-crystal silicon, and alternative channel materials.

Main Results:

• Identified key challenges in M3D integration, particularly the thermal budget for upper active layers.
• Evaluated various material options (polysilicon, single-crystal silicon, alternative channels) for upper layers.
• Highlighted techniques that mitigate thermal degradation of underlying device layers.

Conclusions:

• Successful M3D integration requires overcoming the thermal budget limitations for upper active channel formation.
• Polysilicon, single-crystal silicon, and novel alternative channels offer viable solutions.
• These advancements are crucial for the practical implementation of M3D technology in next-generation electronics.