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A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory.

Kaikai You1, Lei Jin1,2, Jianquan Jia1

  • 1Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China.

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Summary
This summary is machine-generated.

This study introduces "Gate-induced drain leakage (GIDL) pre-charge" to improve 3D NAND flash reliability. This method suppresses program disturbance by enhancing channel potential without structural changes.

Keywords:
3D NAND flashGIDL pre-chargeprogram disturbance

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Area of Science:

  • Electrical Engineering
  • Semiconductor Device Physics
  • Materials Science

Background:

  • Three-dimensional (3D) vertical NAND flash memory faces reliability challenges due to program disturbance.
  • The narrow operational voltage window for unselected word lines (WL) exacerbates Fowler-Nordheim (FN) tunneling.
  • Contradictory voltage requirements for program and inhibited strings complicate disturbance suppression.

Purpose of the Study:

  • To investigate the relationship between channel potential and electron density in 3D NAND.
  • To develop a novel method for mitigating program disturbance in 3D NAND flash memory.
  • To enhance the reliability and operational window of 3D NAND devices.

Main Methods:

  • Systematic analysis of channel potential and electron density dynamics.
  • Introduction of a 'Gate-induced drain leakage (GIDL) pre-charge' scheme.
  • Validation using Technology Computer-Aided Design (TCAD) simulations and real silicon data.

Main Results:

  • The GIDL pre-charge method effectively enhances unselected channel potential by exploiting generated holes.
  • Significantly suppressed program disturbance observed in 3D NAND devices.
  • Demonstrated a larger pass disturb window without altering device structure or operational voltages.

Conclusions:

  • The GIDL pre-charge technique offers a viable solution to program disturbance in 3D NAND.
  • This method improves reliability without requiring new fabrication processes or modified operating parameters.
  • The findings provide a pathway for more robust and dependable NAND flash memory.