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Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks
Riadul Islam1, Patrick Majurski1, Jun Kwon1
1Department of Computer Science and Electrical Engineering, University of Maryland, Baltimore County, Baltimore, MD 21250, USA.
Sensors (Basel, Switzerland)
|February 24, 2024
Summary
Brain-inspired computing, specifically spiking neural networks (SNNs), offers energy efficiency for high-performance computing. This study introduces an automated tool to convert neural networks (NNs) to SNNs, optimizing hardware placement and reducing energy consumption.
Area of Science:
- Computer Science
- Artificial Intelligence
- Neuroscience
Background:
- High-performance computing faces challenges like energy consumption and processor speed limitations.
- Spiking neural networks (SNNs) offer potential for power efficiency but face implementation hurdles.
- Existing methods lack automated tools and efficient algorithms for large-scale SNN deployment on silicon.
Purpose of the Study:
- To develop an automated tool flow for converting any neural network (NN) into a spiking neural network (SNN).
- To introduce a novel graph-partitioning algorithm for efficient SNN placement on network-on-chip (NoC) infrastructure.
- To enable future energy-efficient and high-performance computing paradigms through optimized SNN implementation.
Main Methods:
- Development of an automated tool to transmute artificial neural networks (ANNs) into SNNs.
- Creation of a novel graph-partitioning algorithm for strategic SNN placement on a network-on-chip (NoC).
- Evaluation of the methodology by transforming ANN architectures into SNNs and analyzing communication pathways, latency, and energy consumption.
Main Results:
- Successful transformation of ANN architectures into SNNs with a minimal average error penalty of 2.65%.
- The proposed graph-partitioning algorithm achieved significant reductions in inter-synaptic (14.22%) and intra-synaptic (87.58%) communication.
- Demonstrated average decreases of 79.74% in latency and 14.67% in energy consumption compared to a baseline algorithm.
- Achieved an 82.71% lower average energy-latency product for SNN architectures using existing NoC tools.
Conclusions:
- The developed automated tool flow effectively converts NNs to SNNs, addressing key implementation challenges.
- The novel graph-partitioning algorithm optimizes SNN placement on NoCs, leading to substantial improvements in communication efficiency, latency, and energy consumption.
- This work paves the way for more energy-efficient and high-performance computing systems by facilitating the adoption of SNNs.
