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Updated: Jul 1, 2025

Design and Characterization Methodology for Efficient Wide Range Tunable MEMS Filters
Published on: February 4, 2018
Implementation of distributed arithmetic-based symmetrical 2-D block finite impulse response filter architectures
Pratyusha Chowdari Ch1, J B Seventline2
1Department of Electronics and Communications Engineering, Gokaraju Rangaraju Institute of Engineering and Technology, Hyderabad, 500090, India.
This study introduces an efficient 2-D FIR filter using block processing and symmetries, significantly reducing power and area. The novel architecture optimizes multipliers and memory for enhanced performance in fixed-coefficient applications.
Area of Science:
- Digital Signal Processing
- VLSI Design
- Filter Architectures
Background:
- Efficient implementation of two-dimensional (2-D) Finite Impulse Response (FIR) filters is crucial for various signal processing applications.
- Existing architectures often face challenges in optimizing area, power consumption, and throughput.
- Exploiting filter coefficient symmetries can lead to reduced hardware complexity.
Purpose of the Study:
- To propose and implement efficient 2-D FIR filter architectures utilizing block processing and exploiting filter coefficient symmetries (diagonal and quadrantal).
- To reduce the number of multipliers and optimize memory usage for improved area and power efficiency.
- To evaluate the performance of the proposed architectures compared to existing methods.
Main Methods:
- Development of 2-D FIR filter architectures incorporating block processing for enhanced throughput.
- Utilization of distributed arithmetic (DA)-based multiplication with dual-port memory-based lookup tables (DP-MLUTs) to minimize area and power.
- Implementation using Verilog HDL and synthesis in 45nm technology, with performance analysis including area, delay, and power consumption.
Main Results:
- The proposed architectures demonstrate significant improvements in power, area, Area Delay Product (ADP), and Power Delay Product (PDP) compared to existing designs.
- The 2-D block Quadrantal Symmetry Filter (QSF) with block size 4 achieved reductions of 58.94% in power, 59.5% in area, 48.44% in ADP, and 47.78% in PDP.
- Memory reuse and sharing techniques were employed to reduce register count and circuit complexity.
Conclusions:
- A novel, area-power-efficient DA-based 2-D block FIR filter architecture with symmetries has been successfully realized.
- The incorporation of symmetries and DP-LUT-based multipliers effectively minimizes hardware resources.
- The proposed filter architecture is highly suitable for applications requiring fixed filter coefficients due to its efficiency.
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