Nanoscale Channel Length MoS₂ Vertical Field-Effect Transistor Arrays with Side-Wall Source/Drain Electrodes

Area of Science:

• Materials Science
• Nanotechnology
• Electrical Engineering

Background:

• Two-dimensional transition metal dichalcogenides (TMDCs), like MoS₂, offer advantages for overcoming short-channel effects in field-effect transistors (FETs).
• Existing fabrication methods for sub-100 nm MoS₂ FETs often rely on mechanically exfoliated materials and electron beam lithography (EBL), limiting scalability for integrated circuits (ICs).
• There is a need for scalable fabrication techniques for TMDC-based FETs to enable high-density and low-power IC applications.

Purpose of the Study:

• To design and fabricate MoS₂ FET arrays with vertically distributed side-wall source and drain electrodes.
• To demonstrate a fabrication process free from EBL suitable for wafer-scale device arrays.
• To evaluate the performance and reliability of these vertical MoS₂ FETs for potential use in ICs.

Main Methods:

• Fabrication of MoS₂ FET arrays utilizing a vertical electrode design where channel length is determined by an insulating layer thickness.
• Characterization of the on/off ratios and performance at low drain-source voltage (V_DS).
• Statistical analysis of device yield and performance consistency across fabricated arrays.

Main Results:

• The fabricated vertical MoS₂ FETs achieved on/off ratios comparable to mechanically exfoliated counterparts with nanoscale channels.
• Devices operated effectively at a low V_DS of 10 mV, exhibiting a desirable on/off ratio up to 1.9 × 10⁷, indicating potential for low-power applications.
• The EBL-free fabrication process resulted in a high device yield of 87.5% for the FET arrays, with an average on/off ratio of 1.7 × 10⁶ at 10 mV V_DS.

Conclusions:

• The developed vertical electrode structure and EBL-free fabrication method are effective for producing high-density MoS₂ FET arrays.
• The results demonstrate the feasibility of using TMDCs for fabricating reliable, high-performance, low-power nanoelectronic devices suitable for ICs.
• This approach offers a promising pathway for advancing wafer-scale integration of advanced semiconductor devices.