Vertically Stacked Indium Gallium Zinc Oxide-Based Three-Dimensional Integrated Circuits

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Physics

Background:

• Monolithic 3D (M3D) integration offers advantages over planar architectures for advanced integrated circuits.
• Amorphous oxide semiconductors are suitable for M3D due to room-temperature deposition and uniformity.
• Developing high-performance, multi-tier oxide transistors compatible with existing technologies is a significant challenge.

Purpose of the Study:

• To present a threshold voltage modulation strategy for indium gallium zinc oxide (IGZO) transistors.
• To enable the fabrication of high-performance, multi-tier oxide transistors for 3D integrated circuits.
• To demonstrate functional computing-in-memory 3D circuits using these advanced transistors.

Main Methods:

• Threshold voltage modulation of IGZO transistors through channel thickness control.
• Surface modification using atomic-layer deposition.
• Sequential layer-by-layer integration of a four-tier vertically stacked IGZO transistor array.
• Fabrication of via-hole interconnects for circuit integration.

Main Results:

• Optimized IGZO transistors achieved a low subthreshold swing of 150 mV/dec.
• Achieved an on/off ratio exceeding 10⁸ for the transistors.
• Demonstrated functional computing-in-memory 3D circuits, including inverter modules and dynamic random access memory (DRAM) components.

Conclusions:

• The developed threshold voltage modulation strategy is effective for high-performance IGZO transistors in M3D integration.
• The successful fabrication of a four-tier transistor array and functional 3D circuits validates the approach.
• This work significantly advances the application of oxide semiconductors in future advanced 3D integrated circuits.