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Related Experiment Video

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In Situ Transmission Electron Microscopy with Biasing and Fabrication of Asymmetric Crossbars Based on Mixed-Phased a-VOx

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High-density via RRAM cell with multi-level setting by current compliance circuits.

Yu-Cheng Hsieh¹, Yu-Cheng Lin¹, Yao-Hung Huang¹

¹Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan.

|March 25, 2024

Summary

This study demonstrates multi-level storage in via resistive random-access memory (RRAM) using standard FinFET CMOS logic. New circuits ensure stable resistance control, improving multi-level state stability and distribution for advanced memory applications.

Keywords:

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Area of Science:

Solid-state device physics
Non-volatile memory technologies
Advanced semiconductor manufacturing

Background:

Resistive random-access memory (RRAM) offers high density and low power consumption for non-volatile memory.
Achieving stable multi-level storage in RRAM is crucial for increasing memory capacity.
Standard CMOS logic processes are desirable for integrating novel memory devices.

Purpose of the Study:

To report and demonstrate multi-level storage capabilities in via RRAM for the first time.
To develop and validate novel current compliance setting circuits for stable resistance control.
To improve the stability and tighten the distribution of multi-level states in via RRAM.

Main Methods:

Implementation of multi-level storage in via RRAM using a standard FinFET CMOS logic process.
Control of multi-level states by precisely managing current compliance during set operations.
Design and integration of new current compliance setting circuits to mitigate process variation effects.

Main Results:

Successful demonstration of multi-level storage in via RRAM.
Achieved stable resistance control through proposed current compliance setting circuits.
Observed improved stability and tightened distributions for multi-level states in via RRAM cells.

Conclusions:

Multi-level storage is feasible and demonstrated in via RRAM within a standard FinFET CMOS logic process.
The proposed current compliance circuits effectively enhance the stability and reliability of multi-level states.
This work paves the way for higher-density non-volatile memory solutions based on via RRAM technology.