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Network Function of a Circuit01:25

Network Function of a Circuit

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Frequency response analysis in electrical circuits provides vital insights into a circuit's behavior as the frequency of the input signal changes. The transfer function, a mathematical tool, is instrumental in understanding this behavior. It defines the relationship between phasor output and input and comes in four types: voltage gain, current gain, transfer impedance, and transfer admittance. The critical components of the transfer function are the poles and zeros.
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Biasing of FET01:22

Biasing of FET

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Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
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Fast Decoupled and DC Powerflow01:24

Fast Decoupled and DC Powerflow

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The fast decoupled power flow method addresses contingencies in power system operations, such as generator outages or transmission line failures. This method provides quick power flow solutions, essential for real-time system adjustments. Fast decoupled power flow algorithms simplify the Jacobian matrix by neglecting certain elements, leading to two sets of decoupled equations:
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Neural Circuits01:25

Neural Circuits

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Neural circuits and neuronal pools are two of the main structures found in the nervous system. Neural circuits are networks of neurons that work together to carry out a specific task or process. They consist of interconnected neurons and glial cells, which provide structural and metabolic support.
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Design Example: Capacitance Multiplier Circuit01:20

Design Example: Capacitance Multiplier Circuit

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In integrated circuit technology, a capacitance multiplier is often utilized to produce a larger capacitance value when a small physical capacitance falls short. This is achieved by a circuit that multiplies capacitance values by a factor of up to 1000, such that a 10-pF capacitor can replicate the performance of a 100-nF capacitor.
The circuit illustrated in Figure 1 below incorporates two op-amps, with the first operating as a voltage follower and the second acting as an inverting amplifier.
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Ampere-Maxwell's Law: Problem-Solving01:17

Ampere-Maxwell's Law: Problem-Solving

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A parallel-plate capacitor with capacitance C, whose plates have area A and separation distance d, is connected to a resistor R and a battery of voltage V. The current starts to flow at t = 0. What is the displacement current between the capacitor plates at time t? From the properties of the capacitor, what is the corresponding real current?
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Related Experiment Video

Updated: Jun 29, 2025

Author Spotlight: Modular Neuronal Networks for Analyzing Brain Functions
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Design of Network-on-Chip-Based Restricted Coulomb Energy Neural Network Accelerator on FPGA Device.

Soongyu Kang1, Seongjoo Lee2,3, Yunho Jung1,4

  • 1School of Electronics and Information Engineering, Korea Aerospace University, Goyang 10540, Republic of Korea.

Sensors (Basel, Switzerland)
|March 28, 2024
PubMed
Summary

This study introduces a scalable network-on-chip (NoC)-based accelerator for restricted Coulomb energy neural networks (RCE-NNs) on edge devices. The novel design significantly improves performance for AI-powered sensor applications in the Internet of Things (IoT).

Keywords:
field-programmable gate arrayinternet of thingsnetwork-on-chiprestricted coulomb energy neural network

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Area of Science:

  • Artificial Intelligence
  • Computer Engineering
  • Internet of Things

Background:

  • Edge-based artificial intelligence (AI) computation is preferred for low-latency Internet of Things (IoT) systems.
  • Restricted Coulomb Energy Neural Networks (RCE-NNs) are suitable for edge devices due to their simple learning and adaptable structure.
  • Existing RCE-NN accelerators face scalability challenges with increasing neuron counts.

Purpose of the Study:

  • To propose a scalable network-on-chip (NoC)-based accelerator for RCE-NNs.
  • To implement and evaluate the proposed accelerator on a field-programmable gate array (FPGA).
  • To address the limitations of previous RCE-NN accelerators in handling a large number of neurons.

Main Methods:

  • Development of a novel RCE-NN accelerator utilizing a network-on-chip (NoC) architecture.
  • Implementation of a hierarchical-star (H-star) topology for efficient neuron management.
  • Design of specialized routers optimized for RCE-NN communication.
  • Deployment and testing on a field-programmable gate array (FPGA) platform.

Main Results:

  • The proposed NoC-based RCE-NN accelerator demonstrates improved scalability with minimal decrease in maximum operating frequency as neuron count increases.
  • A 126.1% increase in maximum operating frequency was observed for the accelerator with 512 neurons compared to prior designs.
  • Significant accelerations were achieved in learning time (up to 54.8%) and recognition time (up to 45.7%) for gas and sign language recognition datasets.

Conclusions:

  • The NoC-based RCE-NN accelerator effectively ensures neural network scalability for edge AI applications.
  • The proposed architecture provides a robust solution for high-performance on-chip learning and real-time recognition in IoT systems.
  • This approach overcomes previous limitations, enabling more complex AI tasks on resource-constrained edge devices.