Optimizing fault tolerance of RAM cell through MUX based modeling and design using symmetries of QCA cells

Extensive research is now being conducted on the design and construction of logic circuits utilizing quantum-dot cellular automata (QCA) technology. This area of study is of great interest due to the inherent advantages it offers, such as its compact size, high speed, low power dissipation, and enhanced switching frequency in the nanoscale domain. This work presents a design of a highly efficient RAM cell in QCA, utilizing a combination of a 3-input and 5-input Majority Voter (MV) gate, together with a 2 × 1 Multiplexer (MUX). The proposed design is also investigated for various faults such as single cell deletion, single cell addition and single cell displacement or misalignment defects. The circuit under consideration has a high degree of fault tolerance. The functionality of the suggested design is showcased and verified through the utilization of the QCADesigner tool. Based on the observed performance correlation, it is evident that the proposed design demonstrates effectiveness in terms of cell count, area, and latency. Furthermore, it achieves a notable improvement of up to 76.72% compared to the present configuration in terms of quantum cost. The analysis of energy dissipation, conducted using the QCAPro tool, is also shown for various scenarios. It is seen that this design exhibits the lowest energy dispersion, hence enabling the development of ultra-low power designs for diverse microprocessors and microcontrollers.