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Area of Science:

  • Computer Engineering
  • Hardware Acceleration
  • Parallel Computing

Background:

  • Open Computing Language (OpenCL) enables cross-architecture compatibility.
  • Field Programmable Gate Arrays (FPGAs) offer high-speed computation acceleration.

Purpose of the Study:

  • Investigate memory access time's impact on FPGA performance.
  • Develop benchmarks for assessing FPGA memory behaviors.
  • Define an FPGA abstraction for tailored primitive implementation.

Main Methods:

  • Created eight OpenCL benchmarks for FPGA environments.
  • Analyzed memory access patterns and performance.
  • Explored data workload characteristics.
  • Delineated primitive implementations for FPGAs.

Main Results:

  • Identified memory access time as a critical performance factor.
  • Demonstrated the effectiveness of a task-parallel model.
  • Showcased tailored primitive implementations for FPGAs.
  • Provided insights into FPGA memory system behavior.

Conclusions:

  • OpenCL facilitates FPGA performance analysis.
  • Task-parallel models mitigate synchronization costs on FPGAs.
  • The study contributes to FPGA abstraction and tailored design.