Van der Waals polarity-engineered 3D integration of 2D complementary logic

Area of Science:

• Materials Science
• Condensed Matter Physics
• Nanotechnology

Background:

• Vertical three-dimensional integration of 2D semiconductors offers potential for scaling logic layers.
• Previous limitations in controllable doping schemes for 2D materials have hindered the development of complementary logic circuits.
• Existing methods for doping 2D semiconductors are often unstable or destructive.

Purpose of the Study:

• To develop a stable and non-destructive doping scheme for 2D semiconductors.
• To enable the bottom-up scaling of complementary logic circuitries using 2D materials.
• To demonstrate the feasibility of vertically integrated 3D logic circuits based on polarity-engineered 2D channels.

Main Methods:

• Utilizing van der Waals (vdW) interfacial coupling between MoS2 and chromium oxychloride (CrOCl).
• Reconfiguring the carrier polarity in MoS2 from n-type to p-type via strong vdW coupling.
• Fabricating and characterizing vertical complementary field-effect transistors (CFETs) and integrated logic circuits.

Main Results:

• Achieved room-temperature hole mobilities up to 425 cm^2 V^-1 s^-1 and on/off ratios of 10^6.
• Demonstrated air-stable performance for over one year.
• Successfully constructed vertically integrated complementary logic circuits, including inverters, NANDs, and SRAMs, with multiple vdW layers.

Conclusions:

• The vdW interfacial coupling approach provides a robust and universal method for polarity engineering in 2D semiconductors.
• This technique overcomes doping limitations, paving the way for advanced 3D vertically integrated circuits.
• The findings offer a new direction for the future of 2D logic gate-based integrated electronics.