Search research articles

ABOUT JoVE

Overview Leadership Blog JoVE Help Center

AUTHORS

Publishing Process Editorial Board Scope & Policies Peer Review FAQ Submit

LIBRARIANS

Testimonials Subscriptions Access Resources Library Advisory Board FAQ

RESEARCH

JoVE Journal Methods Collections JoVE Encyclopedia of Experiments Archive

EDUCATION

JoVE Core JoVE Business JoVE Science Education JoVE Lab Manual Faculty Resource Center Faculty Site

Terms & Conditions of Use

Related Concept Videos

Biasing of FET

Biasing of FET

Biasing a Junction Field Effect Transistor (JFET) is crucial for setting operational parameters and ensuring efficient functioning in electronic circuits. JFETs are characterized by using a single carrier type in N-channel or P-channel configurations, where the channel is surrounded by PN junctions. These junctions are central to the device's ability to control current flow.
In an N-channel JFET, the structure consists of N-type material forming the channel on a P-type substrate, with the...

Biasing of P-N Junction

Biasing of P-N Junction

The operation of a p-n junction diode involves various biasing conditions, including forward bias, reverse bias, and equilibrium.
In equilibrium, no external voltage is applied across the p-n junction. The depletion region is formed at the junction interface due to the diffusion of carriers, which leaves behind charged dopants, acceptors on the p-side, and donors on the n-side. These immobile charges create an electric field that prevents further diffusion of carriers. The related energy band...

MOSFET: Enhancement Mode

MOSFET: Enhancement Mode

Enhancement-mode MOSFETs are pivotal components in electronics, distinguished by their capacity to act as highly efficient switches. They are part of the larger family of metal-oxide Semiconductor Field-Effect Transistors (MOSFETs). They are available in two types: p-channel and n-channel, each tailored to specific polarity operations.
In their basic form, enhancement-mode MOSFETs are typically non-conductive when the gate-source voltage (Vgs) is zero. This default 'off' state means no...

Biasing of Metal-Semiconductor Junctions

Biasing of Metal-Semiconductor Junctions

Biasing metal-semiconductor junctions involves applying a voltage across the junction. Specifically, the metal is connected to a voltage source, while the semiconductor is grounded. This technique is essential for controlling the direction and magnitude of current flow in electronic devices, including diodes, transistors, and photovoltaic cells.
In Schottky junctions, where the semiconductor is n-type, applying a positive voltage to the metal relative to the semiconductor reduces its Fermi...

Metal-Semiconductor Junctions

Metal-Semiconductor Junctions

The contact of metal and semiconductor can lead to the formation of a junction with either Schottky or Ohmic behavior.
Schottky Barriers
Schottky barriers arise when a metal with a work function (Φm) contacts a semiconductor with a different work function (Φs). Initially, electrons transfer until the Fermi levels of the metal and semiconductor align at equilibrium. For instance, if Φm > Φs, the semiconductor Fermi level is higher than the metal's before contact. The...

P-N junction

P-N junction

A p-n junction is formed when p-type and n-type semiconductor materials are joined together. At the interface of the p-n junction, holes from the p-side and electrons from the n-side begin to diffuse into the opposite sides due to the concentration gradient. This diffusion of carriers leads to a region around the junction where there are no free charge carriers, known as the depletion region. The charge density within the depletion region for the n-side and p-side can be described by the...

You might also read

Related Articles

Articles linked to this work by shared authors, journal, and citation graph.

Sort by

Same author

Size control of InP nanowires by<i>in situ</i>annealing and its application to the formation of InAsP quantum dots.

Nanotechnology·2024

Same author

Selective-Area Growth of Vertical InGaAs/GaSb Core-Shell Nanowires on Silicon and Dual Switching Properties.

ACS nano·2023

Same author

Creation of unexplored tunnel junction by heterogeneous integration of InGaAs nanowires on germanium.

Scientific reports·2022

See all related articles

Search research articles

Related Experiment Video

Updated: Jun 25, 2025

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

Published on: November 1, 2013

InP Crystal Phase Heterojunction Transistor with a Vertical Gate-All-Around Structure.

Yu Katsumi^1,2, Hironori Gamo^1,2, Junichi Motohisa^1,2

¹Graduate School of Information Science and Technology, Hokkaido University, North 14 West 9, Sapporo 060-0814, Japan.

ACS Applied Materials & Interfaces

|May 31, 2024

Summary

This summary is machine-generated.

Crystal phase heterojunctions (CPHJs) in III-V semiconductors enable novel vertical transistors. This new approach offers improved gate control and high currents, advancing transistor technology beyond 2D materials.

Keywords:

InP crystal phase nanowire selective-area growth vertical transistor wurtzite

More Related Videos

Preparation of Large-area Vertical 2D Crystal Hetero-structures Through the Sulfurization of Transition Metal Films for Device Fabrication

Preparation of Large-area Vertical 2D Crystal Hetero-structures Through the Sulfurization of Transition Metal Films for Device Fabrication

Published on: November 28, 2017

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Published on: August 2, 2019

Related Experiment Videos

Last Updated: Jun 25, 2025

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

Nanofabrication of Gate-defined GaAs/AlGaAs Lateral Quantum Dots

Published on: November 1, 2013

Preparation of Large-area Vertical 2D Crystal Hetero-structures Through the Sulfurization of Transition Metal Films for Device Fabrication

Preparation of Large-area Vertical 2D Crystal Hetero-structures Through the Sulfurization of Transition Metal Films for Device Fabrication

Published on: November 28, 2017

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Published on: August 2, 2019

Area of Science:

Materials Science
Condensed Matter Physics
Semiconductor Device Physics

Background:

Crystal phase heterojunctions (CPHJs) are formed by different atomic arrangements within the same material.
CPHJs offer unique band engineering possibilities without critical thickness or misfit dislocation issues.
Previous CPHJ applications in 2D transition-metal dichalcogenides faced scalability limitations.

Purpose of the Study:

To demonstrate a transistor utilizing CPHJ in conventional III-V semiconductors with a vertical gate-all-around structure.
To overcome the geometrical limitations of in-plane CPHJ devices for improved scalability.
To explore a new switching mechanism and device design for transistors.

Main Methods:

Fabrication of a CPHJ using wurtzite InP nanowires on zincblende InP substrates.
Characterization of the heterojunction's atomic structure and band alignment.
Electrical testing of the CPHJ transistor performance, including gate controllability and current characteristics.

Main Results:

An atomically flat CPHJ was successfully formed without dislocations.
A Type-II band discontinuity was observed across the wurtzite/zincblende InP heterojunction.
The CPHJ transistor exhibited moderate to good gate electrostatic controllability, high on-state currents, and high transconductance.

Conclusions:

CPHJs in III-V semiconductors enable vertical transistors with enhanced performance.
This approach provides a scalable alternative to 2D CPHJ devices.
CPHJs represent a significant advancement in transistor design and switching mechanisms.