The SpinBus architecture for scaling spin qubits with electron shuttling

Area of Science:

• Quantum computing
• Semiconductor physics
• Quantum information science

Background:

• Scaling quantum processors requires high qubit numbers, 2D connectivity, and high fidelities.
• Current semiconductor spin qubits face wiring and crosstalk limitations.
• Electron shuttling offers a potential solution for improved connectivity and reduced crosstalk.

Purpose of the Study:

• To introduce and validate the SpinBus architecture for scalable semiconductor quantum processors.
• To demonstrate the feasibility of electron shuttling for qubit interconnects.
• To achieve high-fidelity operations exceeding 99.9%.

Main Methods:

• Device simulations on the Si/SiGe platform.
• Modeling electron shuttling for qubit connection.
• Assessing qubit coherence and fidelity metrics.

Main Results:

• Simulations confirm SpinBus feasibility using established semiconductor technology.
• Operation fidelities exceeding 99.9% were achieved.
• The architecture supports at least 144 qubits with room temperature control.

Conclusions:

• The SpinBus architecture, leveraging spin-coherent electron shuttling, addresses scalability challenges in quantum computing.
• This approach offers enhanced qubit coherence and reduced crosstalk.
• SpinBus provides a viable foundation for future spin-based quantum processors.