A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital...

Area of Science:

• Electrical Engineering
• Computer Engineering
• Microelectronics

Background:

• Successive Approximation Analog-to-Digital Converters (SAR ADCs) are crucial for mixed-signal systems.
• Energy efficiency and precision are key performance metrics for SAR ADCs.
• Conventional switching schemes can be energy-intensive and complex.

Purpose of the Study:

• To propose an adjustable and energy-efficient switching scheme for SAR ADCs.
• To reduce the digital-to-analog converter (DAC) switching energy.
• To maintain high performance with minimal common-mode voltage variation.

Main Methods:

• Capacitor-splitting technology
• Common-mode conversion techniques
• Simultaneous switching of reference voltages for positive and negative capacitor arrays

Main Results:

• Reduced DAC switching energy by 96.41% compared to conventional schemes.
• Achieved 54.96 dB SNDR and 61.73 dB SFDR in 10-bit mode with 0.67 μW power consumption.
• Achieved 48.33 dB SNDR and 54.17 dB SFDR in 9-bit mode with 0.47 μW power consumption.
• Demonstrated one-LSB common-mode voltage variation.

Conclusions:

• The proposed switching scheme offers significant energy savings for SAR ADCs.
• The scheme provides adjustable resolution (9-10 bits) with low power consumption.
• This technique is suitable for low-power, high-performance mixed-signal integrated circuits.