A Hardware Security Protection Method for Conditional Branches of Embedded Systems

Area of Science:

• Computer Engineering
• Cybersecurity
• Embedded Systems Security

Background:

• Branch prediction units (BPUs) in embedded systems are vulnerable to security exploits.
• Existing protection methods fail to prevent sophisticated attacks like branch prediction analysis (BPA).
• Tampering with branches can lead to control flow integrity (CFI) violations and critical data theft.

Purpose of the Study:

• To propose a novel hardware security protection method for conditional branches in embedded systems.
• To enhance the security of branch prediction units against various attack vectors.
• To ensure control flow integrity and protect sensitive branch information.

Main Methods:

• Implementing a threshold-based mechanism to lock the branch target buffer (BTB) after a set number of updates.
• Designing a hybrid arbiter physical unclonable function (APUF) circuit for encrypting and decrypting branch details (directions, addresses, indexes).
• Utilizing dynamic and static label comparison for detecting tampering with instruction codes, jump addresses, and directions.

Main Results:

• The proposed method effectively resists branch prediction analysis (BPA) attacks by locking the BTB.
• The hybrid APUF circuit enhances randomness and defends against machine learning attacks targeting branch information.
• Fine-grained security protection for conditional branches was achieved with approximately 5.4% resource overhead and less than 5.5% performance overhead on FPGA.

Conclusions:

• The developed hardware security method provides robust protection for conditional branches in embedded systems.
• The approach successfully mitigates known vulnerabilities in BPUs and enhances overall system security.
• The solution is practical for embedded applications, balancing security with acceptable performance and resource overhead.