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Efficient Data Transfer and Multi-Bit Multiplier Design in Processing in Memory.

Jingru Sun1,2, Zerui Li2, Meiqi Jiang2

  • 1Chongqing Research Institute, Hunan University, Chongqing 401120, China.

Micromachines
|June 27, 2024
PubMed
Summary
This summary is machine-generated.

This study introduces a novel memristor-based Processing in Memory design. It enhances data transmission and multi-bit multipliers for efficient computation, reducing latency and power consumption.

Keywords:
MPUPiMaddercrossbar arraymemristormultiplier

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Area of Science:

  • Computer Engineering
  • Materials Science

Background:

  • The Von Neumann bottleneck limits computational efficiency in traditional architectures.
  • Processing in Memory (PIM) using memristors offers a promising solution to this bottleneck.
  • Efficient data transmission and logical computation are critical for PIM performance.

Purpose of the Study:

  • To propose a design for efficient data transmission and multi-bit multipliers in memristor-based PIM.
  • To enhance the execution efficiency of logical operations and in-memory data transfer.
  • To reduce latency and power consumption in memristive computing systems.

Main Methods:

  • Utilizing a memristive alternating crossbar array structure.
  • Reserving edge rows/columns as assistant cells for OR-AND (OA) and AND data transmission logic operations.
  • Converting multipliers into multi-bit addition operations using Multiple Input Multiple Output (MIMO) logical operations.

Main Results:

  • Reduced data transfer steps through optimized assistant cell usage.
  • Improved multiplier execution efficiency via MIMO logical operations.
  • PSpice simulations demonstrate lower latency, reduced power consumption, and higher efficiency and flexibility.

Conclusions:

  • The proposed design effectively addresses data transmission and multi-bit multiplier challenges in memristor-based PIM.
  • This approach significantly enhances computational efficiency and reduces energy consumption.
  • The design offers a flexible and efficient solution for next-generation computing architectures.