A 62.2dB SNDR Event-Driven Level-Crossing ADC With SAR-Assisted Delay Compensation Loop for Time-Sparse Biomedical...

This paper proposed an event-driven clockless level-crossing ADC (LC-ADC) suitable for biomedical applications. Thanks to the LC loop, the sampling rate of the converter automatically adapts to the input activities. Activity-dependent power consumption and data compression can thus be realized, saving system power, especially during time-sparse signal acquisition. Meanwhile, a SAR-assisted loop is exploited to resolve the loop-delay-induced distortion in conventional LC-ADC. Therefore, the resolution and power efficiency of the LC-ADC are improved effectively while maintaining the event-driven feature. Implemented in a 55nm process, the proposed LC-ADC achieves a scalable power consumption and a peak SNDR of 62.2dB for a 20kHz input. It also achieves a Walden FoM of 29.7fJ/conv.-step and a Schreier FoM of 158.6dB, which is best in class, without using off-chip calibration. Sub µW power is realized when the input frequency is below 1.5kHz. The proposed LC-ADC is also verified by simulated electrocardiogram (ECG), neural spike, and electromyogram (EMG) signals. It provides a ∼7X data compression for ECG input, providing an attractive solution for time-sparse signal acquisition in biomedical applications.