High-density vertical sidewall MoS₂ transistors through T-shape vertical lamination.

Area of Science:

• Materials Science
• Nanotechnology
• Semiconductor Device Physics

Background:

• Vertical transistors offer potential for high-density integration but face fabrication challenges.
• Conventional lateral fabrication processes are incompatible with vertical device architectures.
• Achieving high device density in vertical transistors remains a significant hurdle in semiconductor research.

Purpose of the Study:

• To develop a novel fabrication method for high-density vertical transistors.
• To overcome the incompatibility between planar fabrication processes and vertical device structures.
• To demonstrate scalable fabrication of vertical sidewall transistor arrays.

Main Methods:

• A T-shape lamination approach was developed, involving pre-fabrication of lateral transistors on planar substrates.
• Lateral transistors were subsequently laminated onto vertical substrates using T-shape stamps.
• Scalable fabrication was demonstrated through simultaneous lamination and multi-cycle layer-by-layer lamination.

Main Results:

• Successfully realized high-density vertical sidewall transistors using the T-shape lamination technique.
• Vertically stacked 60 MoS2 transistors within a small footprint, achieving a device density exceeding 10^8 cm^-2.
• Demonstrated scalable fabrication methods for creating vertical transistor arrays.

Conclusions:

• The T-shape lamination approach provides a viable solution for fabricating high-density vertical transistors.
• This technique overcomes critical fabrication incompatibilities, paving the way for advanced 3D integrated circuits.
• The demonstrated scalability supports the potential for large-scale manufacturing of vertical transistor arrays.