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Related Experiment Video

Updated: Jul 10, 2026

Residue-Free Fabrication of van der Waals Heterostructures of Two-Dimensional Materials
04:57

Residue-Free Fabrication of van der Waals Heterostructures of Two-Dimensional Materials

Published on: July 18, 2025

Self-cleaning van der Waals lamination for two-dimensional electronics.

Chang Liu1, Shuimei Ding2, Xudong Wang3

  • 1State Key Laboratory of Infrared Physics, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China; College of Semiconductors (College of Integrated Circuits), Hunan University, Changsha 410082, China.

Science Bulletin
|July 8, 2026
PubMed

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Summary
This summary is machine-generated.

A new elastic bevel stamp-assisted thermal lamination (EBTL) method achieves ultra-clean interfaces for two-dimensional (2D) electronics by actively expelling contaminants. This technique enables high-yield fabrication of high-performance 2D stacked devices and complex integrated circuits.

Area of Science:

  • Materials Science
  • Nanotechnology
  • Electronics Engineering

Background:

  • Van der Waals (vdW) lamination is crucial for 2D electronics and 3D integration.
  • Achieving ultra-clean interfaces free from molecular contaminants is a major challenge in vdW stacking.

Purpose of the Study:

  • To introduce a novel elastic bevel stamp-assisted thermal lamination (EBTL) technology.
  • To enable the fabrication of pristine vdW interfaces for advanced 2D electronic devices.

Main Methods:

  • Utilized an elastic bevel stamp-assisted thermal lamination (EBTL) technique at 150 °C.
  • Employed nanomechanical analysis to optimize bevel stamp parameters (angle, size) for large-scale, damage-free lamination.
  • Demonstrated the expulsion of interlayer molecular impurities like water and oxygen.
Keywords:
Clean interfacesClean transferTwo-dimensional materialsVan der Waals heterostructuresVan der Waals lamination

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Last Updated: Jul 10, 2026

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Main Results:

  • Achieved ultra-clean vdW interfaces by actively self-expelling molecular impurities, eliminating bubbles, wrinkles, and defects.
  • Obtained an average interface yield exceeding 95% for ultra-clean 2D stacked structures.
  • Fabricated high-performance devices, including hysteresis-free hBN top-gate transistors (∼10 mV) and ultrafast hetero-diodes (470 ns).
  • Successfully laminated wafer-scale monolayers, twisted bilayers, complex superlattices, and integrated 2D channels, 3D metals, and dielectrics.
  • Demonstrated a fully vdW-laminated 2D transistor array (2400 transistors) with low device-to-device variability.

Conclusions:

  • EBTL technology provides a robust and scalable method for fabricating pristine vdW interfaces.
  • The developed technique significantly enhances the performance and reliability of 2D electronic devices.
  • This approach paves the way for clean vdW integration and the development of high-performance 3D integrated electronic systems.