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Implementation and optimization of SpMV algorithm based on SW26010P many-core processor and stored in BCSR format.

Mengfei Ma1, Xianqing Huang2,3, Jiali Xu1,4

  • 1Information Research Department, Qingdao Marine Science and Technology Center, Qingdao, China.

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|July 17, 2024
PubMed
Summary

This study optimizes sparse matrix-vector multiplication (SpMV) on the SW26010P many-core processor. New strategies significantly accelerate SpMV computations, achieving up to 38x speedup.

Keywords:
Block compressed sparse rowCaching algorithmHigh performance computingSW26010PSparse matrix–vector multiplication

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Area of Science:

  • High-performance computing
  • Parallel processing
  • Computational science

Background:

  • Irregular sparse matrix distributions hinder data access efficiency on many-core architectures like the SW26010P.
  • Implementing sparse matrix-vector multiplication (SpMV) efficiently presents significant challenges due to processor architecture.

Purpose of the Study:

  • To develop and evaluate optimization strategies for SpMV on the SW26010P many-core processor.
  • To address the low data access efficiency caused by irregular sparse matrix structures.

Main Methods:

  • Implemented a memorized data storage transformation strategy, converting CSR to Block Compressed Sparse Row (BCSR) format.
  • Introduced dynamic task scheduling for load balancing across slave cores.
  • Optimized Local Data Memory (LDM) and slave core dual cache strategies.

Main Results:

  • Tested with numerous sparse matrices from the Matrix Market.
  • Demonstrated significant speedup in sparse matrix processing across various matrix sizes.
  • Achieved a master-slave speedup ratio of up to 38 times.

Conclusions:

  • The proposed optimization scheme effectively enhances SpMV performance on the SW26010P processor.
  • The strategies offer a viable solution for accelerating sparse matrix computations in complex applications.
  • This work has broad implications for optimizing other computational tasks on SW26010P many-core systems.