Unlocking High-Performance, Ultra-Low Power van der Waals Photo-Transistors: Toward Back-End-of-Line in-Sensor...

Recent reports on machine learning and machine vision (MV) devices have demonstrated the potential of two-dimensional (2D) materials and devices. Yet, scalable 2D devices are being challenged by contact resistance and Fermi level pinning (FLP), power consumption, and low-cost CMOS compatible lithography processes. To enable CMOS + 2D, it is essential to find a proper lithography strategy that can fulfill these requirements. Here, we explored a modified van der Waals (vdW) deposition lithography and demonstrated a relatively new class of van der Waals field effect transistors (vdW-FETs) based on 2D materials. This lithography strategy enabled us to unlock high-performance devices evident by high current on-off ratio (I_on/I), high turn-on current density (I_on), and weak FLP. We utilized this approach to demonstrate a gate-tunable near-ideal diode using a MoS₂/WSe₂ heterojunction with an ideality factor of ∼1.65 and current rectification of 10². We finally demonstrated a highly sensitive, scalable, and ultralow power phototransistor using a MoS₂/WSe₂ vdW-FET for back-end-of-line integration. Our phototransistor exhibited the highest gate-tunable photoresponsivity achieved to date for white light detection with ultralow power dissipation, enabling ultrasensitive optoelectronic applications such as in-sensor MV. Our approach showed the great potential of modified vdW deposition lithography for back-end-of-line CMOS + 2D applications.