Efficient Modeling of Single Event Transient Effect with Limited Peak Current: Implications for Logic Circuits

Area of Science:

• Electrical Engineering
• Computer Engineering
• Semiconductor Physics

Background:

• Conventional double-exponential (DE) models can overestimate soft error rates (SER) in logic cells due to circuit overdriving.
• Accurate SER prediction is crucial for reliable integrated circuit design.

Purpose of the Study:

• To introduce and validate a new piecewise double-exponential transient current model (PDE model) for accurate SER prediction.
• To address the overestimation problem associated with the DE model.

Main Methods:

• Developed and implemented the PDE model for characterizing transient current pulses.
• Utilized TCAD (Technology Computer-Aided Design) models from a 28 nm process library and cell layouts.
• Calibrated device transfer characteristic curves and performed functional timing verification.
• Employed the Layout Awareness Single Event Multi Transients Soft Error Rate Calculation (LA-SEMT-SER) tool to assess SER.

Main Results:

• The PDE model demonstrated better consistency with TCAD simulations for single event transient currents compared to the DE model.
• SER calculations using the PDE model with the LA-SEMT-SER tool showed a smaller error than those using the DE model.

Conclusions:

• The PDE model provides a more accurate approach to SER prediction by piecewise characterization and peak current limitation.
• This improved accuracy leads to more reliable estimations of logic cell soft error rates, enhancing circuit design.