A Study on Dual-Gate Dielectric Face Tunnel Field-Effect Transistor for Ternary Inverter.

Area of Science:

• Semiconductor device physics
• Advanced materials science

Background:

• Ternary logic systems require specialized transistors capable of multiple stable output states.
• Existing field-effect transistors often lack the necessary characteristics for efficient ternary operations.

Purpose of the Study:

• To propose and analyze a dual-gate dielectric face tunnel field-effect transistor (DGDFTFET) for ternary logic applications.
• To define and evaluate key performance indicators for DGDFTFETs in ternary inverters.
• To demonstrate the superior performance of DGDFTFETs compared to conventional face tunnel field-effect transistors (FTFETs).

Main Methods:

• Device fabrication and characterization of the proposed DGDFTFET.
• Development of four key performance indicators tailored for ternary operations.
• Analysis of voltage transfer characteristics (VTCs) and static noise margins (SNMs) of ternary inverters.
• Comparative analysis between DGDFTFET and FTFET performance metrics.

Main Results:

• The DGDFTFET successfully exhibits three distinct output voltage states, crucial for ternary logic.
• Proposed performance indicators correlate directly with ternary inverter efficiency.
• Ternary inverters utilizing DGDFTFETs show improved VTCs with three stable levels and enhanced SNMs.
• DGDFTFETs demonstrate significantly superior performance over FTFETs based on key indicators and SNM.

Conclusions:

• The DGDFTFET is a promising candidate for realizing efficient ternary logic circuits.
• Optimizing DGDFTFET design parameters leads to enhanced ternary inverter performance.
• The proposed device architecture offers a substantial advancement over existing FTFET technology for multi-valued logic.