Scalable Multi-FPGA HPC Architecture for Associative Memory System.

Area of Science:

• Computational Neuroscience
• Hardware Acceleration
• Artificial Intelligence

Background:

• Associative memory is crucial for human cognitive intelligence.
• Bayesian confidence propagation neural networks (BCPNNs) effectively model associative memory but face scalability challenges with GPUs.
• Current GPU-based simulations of BCPNNs exhibit limitations in latency and power efficiency as model size increases.

Purpose of the Study:

• To propose a scalable multi-FPGA high-performance computing (HPC) architecture for BCPNN-based associative memory.
• To address the latency and power efficiency issues encountered with GPU simulations of large-scale BCPNN models.
• To optimize the architecture for both spatial and temporal scalability in associative memory tasks.

Main Methods:

• Developed a multi-FPGA architecture integrating hypercolumn unit (HCU) cores for online learning and inference.
• Implemented a spike-based synchronization scheme for inter-FPGA communication.
• Employed population-based model mapping, packet-based spike synchronization, and cluster-based timing optimization for multi-FPGA implementation.

Main Results:

• Validated the architecture on two Xilinx Alveo U50 FPGA cards, supporting up to 20,010 neurons at 220 MHz.
• Achieved a maximum scale-latency ratio (SLR) of 268.82 for the two-FPGA implementation.
• Demonstrated significant improvements over a two-GPU system, with a 51.72% latency reduction and over 5.28x power reduction.

Conclusions:

• The proposed multi-FPGA architecture offers a scalable and efficient solution for BCPNN-based associative memory.
• The system demonstrates superior performance in terms of latency, power consumption, and pattern storage capacity compared to GPU counterparts.
• This hardware acceleration approach paves the way for more biologically plausible and efficient neuromorphic computing systems.