Adapting magnetoresistive memory devices for accurate and on-chip-training-free in-memory computing

Area of Science:

• Materials Science: Focus on magnetic tunnel junction (MTJ) devices.
• Computer Engineering: Explores analog in-memory computing (AiMC) architectures.
• Artificial Intelligence: Investigates deep neural network (DNN) acceleration.

Background:

• Memristors are key for efficient multiply-accumulate (MAC) operations in AiMC crossbar arrays.
• Device variations in memristors and circuits hinder analog computing accuracy.
• On-chip training, a common solution, is limited by memristor endurance.

Purpose of the Study:

• To develop a hardware-software codesign for MTJ-based AiMC.
• To achieve software-level accuracy without on-chip training.
• To leverage MTJ's low variability for accurate AI inference.

Main Methods:

• Utilized magnetic tunnel junction (MTJ) devices for AiMC.
• Implemented an off-chip calibration method for MTJ-based AiMC.
• Experimentally evaluated over 1 million mass-produced MTJ devices for cycle-to-cycle variations.
• Developed an off-chip training method to adjust DNN parameters.

Main Results:

• MTJ devices demonstrated ultralow cycle-to-cycle variations.
• The proposed off-chip training achieved accurate AiMC inference.
• Validated improved transfer curve linearity and reduced errors in MAC operations.
• Emulated large-scale neural network models matched software baseline accuracy.

Conclusions:

• The MTJ-based AiMC with off-chip calibration achieves high accuracy without on-chip training.
• This approach overcomes memristor endurance limitations.
• MTJ devices show significant potential for efficient and accurate AI acceleration tasks.