Hardware optimization for effective switching power reduction during data compression in GOLOMB rice coding.

Area of Science:

• VLSI design and testing
• Data compression algorithms
• Hardware acceleration for AI/ML

Background:

• Lossless data compression is critical for VLSI test vector generation, hardware AI/ML computations, and efficient data handling.
• Golomb code offers effective lossless compression but is restricted to divisors that are powers of two.
• Golomb Rice (GR) coding is a variant suitable for geometrically distributed data.

Purpose of the Study:

• To enhance the compression ratio of Golomb Rice (GR) coding by optimizing the encoding of its unary part.
• To reduce the bit usage and hardware resource requirements for GR code encoding.
• To evaluate the performance improvements in terms of compression, delay, area, and power consumption.

Main Methods:

• Developed and implemented an algorithm to further encode the unary part of the Golomb Rice code.
• Coded the algorithm in Verilog and simulated its functionality using Modelsim.
• Synthesized the Verilog code using Cadence Encounter RTL Synthesizer for hardware implementation analysis.

Main Results:

• Achieved a 6% to 19% reduction in bits used for linearly distributed data sets.
• Reduced worst-case delays by 3% to 8%.
• Demonstrated area reduction ranging from 22% to 36% and nearly 7% reduction in switching power consumption.

Conclusions:

• The proposed optimization significantly improves the efficiency of Golomb Rice coding for hardware implementations.
• The enhanced GR coding technique is suitable for VLSI test vector compression and data computation, particularly for geometrically distributed data.
• The optimizations contribute to more efficient hardware for AI/ML computations and data processing.