Parasitic Capacitance in High-Density Neural Electrode Arrays: Sources and Evaluation Methods.

Area of Science:

• Neuroscience
• Materials Science
• Electrical Engineering

Background:

• High-density neural electrode arrays are crucial for advanced brain-computer interfaces.
• Parasitic capacitance is an inherent challenge in miniaturized electrode designs.
• Understanding and quantifying parasitic capacitance is essential for accurate electrochemical measurements.

Purpose of the Study:

• Identify sources of parasitic capacitance in high-density neural electrode arrays.
• Develop methods to evaluate parasitic capacitance values.
• Assess the impact of parasitic capacitance on electrode electrochemical properties.

Main Methods:

• Utilized electrochemical impedance spectroscopy (EIS) and voltage transient (VT) measurements.
• Evaluated a 16-channel ultramicro-sized electrode array (UMEA).
• Compared narrow and wide trace array designs for 20-µm diameter electrodes.

Main Results:

• Capacitive leakage caused a 34% underestimation of charge injection capacity during current pulsing.
• Electrode impedance was underestimated by capacitive leakage at frequencies above 1.5 kHz during EIS.
• Capacitive leakage during cyclic voltammetry (CV) was not significant.

Conclusions:

• Electrode design and insulation thickness significantly influence capacitive leakage.
• Minimizing capacitive leakage is critical for accurate electrochemical characterization of neural electrodes.
• Accurate assessment of parasitic capacitance improves electrode impedance and stimulation threshold estimations.