Quasi-Zero-Dimensional Source/Drain Contact for Fermi-Level Unpinning in a Tungsten Diselenide (WSe₂) Transistor:...

Area of Science:

• Materials Science
• Condensed Matter Physics
• Nanotechnology

Background:

• Two-dimensional (2D) transition metal dichalcogenides (TMDCs) are promising for next-generation electronics due to their unique electrical and optical properties.
• Fermi-level pinning (FLP) at metal-semiconductor contacts restricts Schottky barrier height (SBH) control, limiting 2D TMDC field-effect transistor (FET) polarity.
• Achieving tunable transistor characteristics is crucial for advancing 2D TMDC-based electronic devices.

Purpose of the Study:

• To develop a source/drain (S/D) contact structure that alleviates Fermi-level pinning (FLP) in 2D TMDC FETs.
• To demonstrate controllable transistor polarity by manipulating contact dimensionality.
• To investigate the impact of reduced dimensionality on Schottky barrier height (SBH) and FLP.

Main Methods:

• Fabrication of a novel quasi-zero-dimensional (quasi-0D) contact interface using Ag conductive filaments on WSe2 FETs.
• Characterization of electrical properties, including Schottky barrier height (SBH) and Fermi-level pinning (FLP) factor, for conventional and quasi-0D contacts.
• Schottky barrier modeling to analyze the influence of interface dipoles and dimensionality on FLP.

Main Results:

• Conventional metal contacts on WSe2 FETs exhibited n-type characteristics due to strong FLP (pinning factor of 0.06).
• The proposed quasi-0D contact on WSe2 FETs demonstrated p-type characteristics with an SBH close to the Schottky-Mott rule (pinning factor of 0.95).
• Modeling confirmed that quasi-0D contacts are less susceptible to interface dipoles, reducing FLP and enabling SBH control.

Conclusions:

• The developed quasi-0D contact structure effectively alleviates FLP, enabling controllable transistor polarity in 2D TMDC FETs.
• Reducing contact dimensionality to quasi-0D offers a pathway to overcome FLP and achieve desired device characteristics.
• This approach is highly compatible with the fabrication of scaled-down nanoscale electronic devices.