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Numerical Analysis in Double-Sided Polishing: Mechanism Exploration of Edge Roll-Off
Jiayu Chen1,2,3, Yiran Liu3, Ding Wang1
1School of Materials and Chemistry, University of Shanghai for Science and Technology, Shanghai 200093, China.
Materials (Basel, Switzerland)
|October 16, 2024
Summary
This study reveals how stress concentration during silicon wafer polishing affects edge roll-off and polishing uniformity. Understanding these stress mechanisms is key to improving semiconductor substrate quality and flatness.
Area of Science:
- Materials Science
- Semiconductor Manufacturing
- Mechanical Engineering
Background:
- Improving semiconductor wafer quality is critical for advanced electronics.
- Double-Sided Polishing (DSP) is a key process for achieving wafer flatness.
- Stress concentration effects on silicon wafers during DSP require further mechanistic understanding.
Purpose of the Study:
- To investigate the mechanism of stress concentration during silicon wafer polishing.
- To analyze the impact of contact states and stress on edge roll-off (ERO) and polishing rate uniformity.
- To provide a basis for optimizing DSP process design.
Main Methods:
- Development of a two-dimensional finite element model for polishing simulation.
- Experimental validation of the finite element model.
- Analysis of contact state variations due to wafer thickness and carrier gap.
Main Results:
- Identified six distinct stages of contact states during the polishing process.
- Determined that pad compression at the wafer edge causes stress concentration.
- Observed a threshold stress value that influences ERO, polishing uniformity, and wafer flatness.
Conclusions:
- Stress concentration is a significant factor affecting wafer flatness during DSP.
- Wafer thickness and carrier gap critically influence contact states and stress distribution.
- Optimizing DSP by managing stress concentration can enhance semiconductor substrate quality.
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