Demonstration of a novel majority logic in a memristive crossbar array for in-memory parallel computing.

Area of Science:

• Materials Science
• Computer Engineering
• Nanotechnology

Background:

• Traditional von Neumann computing faces data bottlenecks due to separate memory and processing units.
• Memristive crossbar arrays offer potential for in-memory computing, but reliability and efficiency challenges persist.

Purpose of the Study:

• To develop a universal, reliable, and efficient three-input majority logic gate for memristive logic-in-memory systems.
• To demonstrate the gate's capability for complex arithmetic operations and its potential for scalable computing.

Main Methods:

• Fabrication of a Hafnium Oxide (HfO2)-based memristive array with an integrated series resistor to enhance operational voltage margin.
• Implementation of a three-input majority logic gate for near-memory Boolean operations.
• Experimental validation of 1-bit full adder and subtractor operations using the fabricated array.

Main Results:

• The HfO2-based memristive array demonstrated robust reliability for the majority logic gate.
• Successful experimental proof of combined 1-bit full adder and subtractor operations in 5 steps using 7 cells.
• Proposed an N-bit parallel prefix adder (PPA) operation achievable in O(log2 N) steps, showing 8.5x higher spatiotemporal efficiency than NOR-based systems for 64-bit addition.

Conclusions:

• The developed three-input majority logic gate is a universal gate that enhances reliability and efficiency in memristive logic-in-memory applications.
• The proposed parallel prefix adder architecture significantly improves spatiotemporal efficiency, with performance scaling favorably as N increases.
• This work advances the practical implementation of memristive computing by addressing key challenges in operational performance and scalability.