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Updated: Jun 9, 2025

The Effect of Anodization Parameters on the Aluminum Oxide Dielectric Layer of Thin-Film Transistors
Published on: May 24, 2020
Experimental-Modeling Framework for Identifying Defects Responsible for Reliability Issues in 2D FETs
Luca Panarella1,2, Stanislav Tyaginov2, Ben Kaczer2
1KU Leuven, Celestijnenlaan 200D, Heverlee 3001, Belgium.
Abstract:
In this work, a self-consistent method is used to identify and describe defects plaguing 300 mm integrated 2D field-effect transistors. This method requires measurements of the transfer characteristic hysteresis combined with physics-based modeling of charge carrier capture and emission processes using technology computer aided design (TCAD) tools. The interconnection of experiments and simulations allows one to thoroughly characterize charge trapping/detrapping by/from defects, depending on their energy position. Once the trap energy distribution is extracted, it is used as input in transient TCAD simulations to reproduce the experimental hysteretic transfer characteristics. Our method is widely applicable to any 2D channel/gate stack combination. Here, it is demonstrated on FAB-integrated devices with AlO/HfO2 gate oxide. A Gaussian-approximated defect band in the AlO interlayer centered at a position of about 0.1 eV below the conduction band minimum of WS2 is obtained. Based on this energy position, it is concluded that aluminum interstitial and oxygen vacancies are the defects giving rise to the observed hysteresis. These defects are detrimental to the stability of the studied devices as they are easily accessible by channel carriers during on-state operation. A prominent hysteresis obtained during measurements is consistent with this conclusion.
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