FPGA-based low-light image enhancement using Retinex algorithm and coarse-grained reconfigurable architecture.

Area of Science:

• Digital Imaging and Video Processing
• Computer Engineering
• Image Processing Hardware

Background:

• Low-light conditions degrade image quality in critical sectors like medical imaging and aerospace.
• Existing digital imaging systems struggle with uneven lighting, impacting clarity and safety.
• Need for computationally efficient solutions for real-time low-light image enhancement.

Purpose of the Study:

• To develop a hardware-optimized system for low-light image enhancement.
• To implement the Retinex algorithm on a Field-Programmable Gate Array (FPGA) for improved visual quality.
• To achieve high processing speeds and low latency in challenging lighting environments.

Main Methods:

• Utilized the Retinex algorithm for low-light image enhancement.
• Implemented the system on a Xilinx FPGA using Verilog HDL on a Coarse-Grained Reconfigurable Architecture (CGRA).
• Prioritized hardware optimization for minimal latency and high-quality outputs.

Main Results:

• Achieved a processing rate of 60 frames per second (fps) for 720x576 resolution images.
• Demonstrated significant image quality improvements with a Peak Signal-to-Noise Ratio (PSNR) of 43.18 dB and a Structural Similarity Index (SSIM) of 0.92.
• Exhibited low power consumption (0.186 W) and efficient resource utilization (2.2% Slice LUTs/Registers).

Conclusions:

• The FPGA-based Retinex system offers high computational efficiency for low-light image enhancement.
• The developed system provides significant improvements in image quality and processing speed.
• The solution is highly beneficial for critical applications requiring clear imaging in adverse lighting conditions.