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Charge-trap synaptic device with polycrystalline silicon channel for low power in-memory computing.

Min-Kyu Park¹, Joon Hwang¹, Soomin Kim²

¹Department of Electrical and Computer Engineering with Inter-university Semiconductor Research Center (ISRC), Seoul National University, Seoul, 08826, Republic of Korea.

Scientific Reports

|November 23, 2024

Summary

This study demonstrates a processing-in-memory (PIM) hardware architecture using charge-trap flash (CTF) synaptic devices. This innovative PIM circuit significantly reduces inference energy for efficient neuromorphic computing and image recognition tasks.

Keywords:

Charge-trap flash Hardware neural network Inference Memory wall Off-chip learning Processing-in-memory (PIM)poly-Si channel

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Area of Science:

Computer Engineering
Materials Science
Artificial Intelligence

Background:

The von Neumann bottleneck limits current computing architectures.
Processing-in-memory (PIM) offers a solution by performing computations within memory.
Charge-trap flash (CTF) technology is explored as a promising candidate for synaptic devices in PIM.

Purpose of the Study:

To implement and evaluate a PIM hardware architecture utilizing CTF as a synaptic device.
To assess the performance of the PIM circuit in terms of inference energy reduction.
To investigate the system accuracy, energy efficiency, computing efficiency, and latency for neuromorphic applications.

Main Methods:

Implementation of a PIM hardware circuit using CTF synaptic devices.
Training a Visual Geometry Group (VGG)-8 neural network on the Canadian Institute for Advanced Research (CIFAR)-10 dataset for off-chip learning.
Simulations incorporating device variations, array size, and technology node scaling.

Main Results:

The PIM circuit with CTF memory demonstrated significant reduction in synapse array inference energy.
High image recognition accuracy was achieved using the VGG-8 neural network.
Detailed analysis of energy efficiency, computing efficiency, and latency for the integrated PIM architecture.

Conclusions:

The developed PIM hardware architecture based on CTF synaptic devices effectively addresses the von Neumann bottleneck.
The PIM circuit shows great potential for energy-efficient and high-performance neuromorphic computing applications.
Simulations confirm the viability and scalability of the proposed PIM architecture.