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MOS Capacitor01:25

MOS Capacitor

A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
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CMOS-compatible ferroelectric tunnel junctions integrate stochastic sampling and deterministic computing for image

Ryun-Han Koo1, Jonghyun Ko1, Wonjun Shin2

  • 1Department of Electrical and Computer Engineering and Inter-university Semiconductor Research Center, Seoul National University, Seoul, Republic of Korea.

Nature Communications
|May 8, 2026
PubMed
Summary
This summary is machine-generated.

This study introduces a novel hardware framework using ferroelectric tunnel junctions (FTJs) for efficient generative AI. The FTJ-based system enables both random sampling and precise calculations on a single chip, advancing hardware for image generation.

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Area of Science:

  • Materials Science
  • Computer Engineering
  • Artificial Intelligence

Background:

  • Generative modeling advancements necessitate compact, energy-efficient hardware.
  • Implementing hardware for image generation faces challenges due to conflicting stochastic and deterministic processing needs.

Purpose of the Study:

  • To develop a unified hardware framework for generative AI that integrates stochastic sampling and deterministic decoding.
  • To leverage ferroelectric tunnel junctions (FTJs) for dual-mode hardware operation.

Main Methods:

  • Utilized hafnium-oxide ferroelectric tunnel junctions (FTJs) for a unified hardware framework.
  • Implemented dual-mode operation: random telegraph noise for stochastic sampling and multi-level conductance states for vector-matrix multiplication.
  • Employed CMOS- and VLSI-compatible fabrication techniques.

Main Results:

  • Demonstrated a single device array supporting both stochastic latent space sampling and deterministic decoding.
  • Achieved high-quality image generation (MNIST, CelebA) through voltage and sampling-time tuning of randomness and reliability.
  • Confirmed stable performance over 10^5 cycles.

Conclusions:

  • The FTJ-based framework offers a viable route toward scalable, on-chip generative AI accelerators.
  • This approach overcomes limitations of previous hardware-based generative AI solutions.
  • The technology enables efficient implementation of complex AI tasks directly in hardware.