Defect-mediated generation-recombination dynamics governing conductance response in floating-body transistors

Area of Science:

• Semiconductor Physics
• Materials Science
• Nanotechnology

Background:

• Modern Complementary Metal-Oxide-Semiconductor (CMOS) technologies are advancing towards ultra-thin floating-body architectures.
• Defect-mediated carrier dynamics are becoming increasingly significant in nanoscale transistors, challenging traditional linear models.
• Understanding these defect dynamics is crucial for accurate interpretation of electrical responses.

Purpose of the Study:

• To investigate the conductance response mechanisms in foundry-fabricated floating-body transistors.
• To determine the role of deep-level defects versus interface traps in device behavior.
• To establish a framework for interpreting conductance and noise dynamics in advanced nanoscale devices.

Main Methods:

• Frequency-dependent conductance measurements.
• Temperature-dependent low-frequency noise spectroscopy.
• Electrical stress to induce bias-dependent transitions.

Main Results:

• Conductance response is governed by generation-recombination (GR) dynamics of deep-level defects within the ultra-thin silicon body.
• Bell-shaped conductance responses show weak gate-bias dependence but strong temperature sensitivity, unlike bulk MOSFETs.
• Correlated conductance and noise analysis allowed extraction of defect energetic positions and densities.
• Electrical stress revealed a transition from interface-controlled to channel-defect-controlled dynamics.

Conclusions:

• Conductance measurements in ultra-thin floating-body transistors probe a coupled defect system.
• The observed phenomena are rooted in thermally activated GR processes involving inversion carriers and channel defects.
• A physically grounded framework is provided for understanding conductance and noise in advanced nanoscale transistors.